Developed an on-line diagnostic, aka Checkers, for an edge measurement subsystem in a 1000-pin, mixed-signal, full-functional, high-speed digital ATE chip tester having an accuracy within pico-seconds. Early versions of this diagnostic prior to any hardware were run in the Verilog co-sim environment with Catalyst Image. Also created two modules for an application-level driver for the Edge Measurement Calibration Subsystem (ECMS). One was for the patterns on the calibration channels in the support board containing the edge measurement subsystem. The other was a 3-dimensional, linear regression algorithm for calibrating the Time Control Measurement Unit (TCMU) itself contained within the ECMS. Helped extensively with trouble-shooting hardware, hardware bring-up and software driver support problems and debug.